1. Field of the Invention
It is related to a semiconductor memory device capable of correcting errors in storage data and, more particularly, to a semiconductor memory device capable of changing the ECC (error correction code) code length for error correction.
2. Description of the Related Art
Semiconductor memory devices such as DPAM have come to be increasingly important in the recovery of defective bits in the progression toward larger capacities. Semiconductor memory devices with redundant constitutions in which redundant memory cell arrays are provided and defective memory cells are replaced with redundant memory cells for the recovery of defective bits, have come to be widely used.
In recent years, semiconductor memory devices capable of storage data error correction without substitution with redundant memory cells have been proposed. For example, Japanese Application Laid Open No. 2005-44386 and so forth have been proposed.
This semiconductor memory device capable of storage data error correction comprises, in addition to a memory cell array for storing data, a parity memory cell array that stores parity bits which have been generated from write data. During writing, the semiconductor memory device generates parity bits from input data and stores input data and parity data. During reading, the semiconductor memory device generates parity bits from read data, compares these parity bits with the stored parity bits, generates syndrome data that has error bit information, corrects the error bits on the basis of the syndrome data, and outputs the corrected read data.
In this ECC, with a certain Hamming code, a one-bit error in 8-bit data can be corrected by using parity bits of 4 bits with respect to 8-bit data. Further, by using parity bits of 5 bits for 16-bit data, a one-bit error among the 16 bits can be corrected. Then, generally, a one-bit error among 2N bits can be corrected by using parity bits of N+1 bits for data of 2N bits.
As mentioned earlier, by providing the memory cell array with a parity region in addition to a data region and providing a parity generation circuit and an error correction circuit as peripheral circuits, error correction of defective bits is possible and an increase in the yield as well as the accompanying reduction in costs can be implemented.
However, the error correction capability differs depending on the code length of the ECC and the yield also varies in accordance with error correction capability. A parity bit for N+1 bits is used for the 2N bit data mentioned above. Accordingly, the redundancy of the memory cell array increases as N grows smaller and, when the defect density is low, the high redundancy increases the chip area and a cost increase is incurred. However, when the defect density is high, the defect rescue probability is high and an increase in costs can be suppressed. However, the higher N is, the lower the redundancy of the memory cell array and; when the defect density is low, an increase in costs can be suppressed. However, when the defect density is high, an increase in costs is, conversely, induced because the rescue probability is low as a result of the low error correction capability.
In other words, where the ECC code length is concerned, it is a trade-off between the possibility of an increase in the yield and an increase in the error correction probability afforded by increasing the code length, and an increase in the memory cell array area used for parity bits due to the increased code length and the accompanying enlargement of the chip. Moreover, the relationship changes depending on the defect density.
Therefore, when a semiconductor memory device is designed, the optimum ECC code length must be determined by estimating the magnitude of the defect density. However, this estimation and judgment are not necessarily straightforward.